VHDL FIFO

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library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;

entity FIFO_DEPTH16_32_8 is
	port(	H	  : in std_logic;
		RESET	  : in std_logic;
		LD, RD	  : in std_logic; --load, read
		DATA_IN	  : in std_logic_vector(7 downto 0);
		DATA_OUT  : out std_logic_vector(7 downto 0);
		EMPTY,FULL: out std_logic
	);
end FIFO_DEPTH16_32_8;

architecture behav of FIFO_DEPTH16_32_8 is
	type memory is array (0 to 31) of std_logic_vector(7 downto 0);
	signal MEM : memory;
	
	signal FSTART : integer range 0 to 15; -- indice de debut FIFO
	signal FEND   : integer range 0 to 15; -- indice de fin FIFO
	signal intEMPTY, intFULL : std_logic;
begin
	process(H) is
	begin
		if(H'event AND H='1') then
			if RESET='1' then
				FSTART <= 0;
				FEND <= 0;
				intEMPTY <= '1';
				intFULL <= '0';
				-- il vaut mieux aussi vider MEM. voir mot-cle others sur internet
			end if;
			
			if LD='1' then
				if intFULL='1' then
					null;
				else
					intEMPTY <= '0';
					MEM(FEND) <= DATA_IN;
					if FEND=15 then
						FEND <= 0;
						if FSTART=0 then
							intFULL <= '1';
						end if;
					else
						FEND <= FEND+1;
						if FSTART=FEND+1 then
							intFULL <= '1';
						end if;
					end if;
				end if;
			end if;
			
			if RD='1' then
				if intEMPTY='1' then
					DATA_OUT <= "00000000"; -- pas important
				else
					intFULL <= '0';
					DATA_OUT <= MEM(FSTART);
					if FSTART=15 then
						FSTART <= 0;
						if FEND=0 then
							intEMPTY <= '1';
						end if;
					else
						FSTART <= FSTART+1;
						if FEND=FSTART+1 then
							intEMPTY <= '1';
						end if;
					end if;
				end if;
			else
				DATA_OUT <= "00000000";
			end if;
		end if;
	end process;
	
	EMPTY <= intEMPTY;
	FULL  <= intFULL;
end behav;