VHDL TD 3

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library ieee;
use ieee.std_logic_1164.ALL;

entity basculeD_set_reset is
	port(	H,SET,RESET : in std_logic;
		D	    : in std_logic;
		Q,notQ	    : out std_logic
	);
end basculeD_set_reset;

architecture behav of basculeD_set_reset is
	signal intQ : std_logic;
begin
	process(H, RESET, SET) is
	begin
		if RESET='1' then
			intQ <= '0';
		elsif SET='1' then
			intQ <= '1';
		elsif(H'event and H='1') then
			intQ <= D;
		end if;
	end process;
	
	Q <= intQ;
	notQ <= NOT(intQ);
end behav;

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library ieee;
use ieee.std_logic_1164.ALL;

entity basculeD_reset_enable is
	port(	H,RESET,ENABLE	: in std_logic;
		D		: in std_logic;
		Q,notQ		: out std_logic
	);
end basculeD_reset_enable;

architecture behav of basculeD_reset_enable is
	signal intQ : std_logic;
begin
	process(H) is
	begin
		if(H'event and H='1') then
			if RESET='1' then
				intQ <= '0';
			elsif ENABLE='0' then
				intQ <= D;
			end if;
		end if;
	end process;
	
	Q <= intQ;
	notQ <= NOT(intQ);
end behav;

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library ieee;
use ieee.std_logic_1164.ALL;

entity registre_4bits is
	port(	H,RESET	: in std_logic;
		D	: in std_logic_vector(3 downto 0);
		Q,notQ	: out std_logic_vector(3 downto 0)
	);
end registre_4bits;

architecture behav of registre_4bits is
	signal intQ: std_logic_vector(3 downto 0);
begin
	process(H) is
	begin
		if(H'event and H='1') then
			if RESET='1' then
				intQ <= "0000";
			else
				intQ <= D;
			end if;
		end if;
	end process;
	
	Q <= intQ;
	notQ <= NOT(intQ);
end behav;

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library ieee;
use ieee.std_logic_1164.ALL;

entity basculeD_reset is
	port(	H,RESET	: in std_logic;
		D	: in std_logic;
		Q,notQ	: out std_logic
	);
end basculeD_reset;

architecture behav of basculeD_reset is
	signal intQ : std_logic;
begin
	process(H) is
	begin
		if(H'event and H='1') then
			if RESET='1' then
				intQ <= '0';
			else
				intQ <= D;
			end if;
		end if;
	end process;
	Q <= intQ;
	notQ <= NOT(intQ);
end behav;

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library ieee;
use ieee.std_logic_1164.ALL;

entity basculeT is
	port(	H,RESET	: in std_logic;
		Q	: out std_logic
	);
end basculeT;

architecture behav of basculeT is
	component basculeD_reset is
		port(	H,RESET	: in std_logic;
			D	: in std_logic;
			Q,notQ	: out std_logic
		);
	end component;
	
	signal aux : std_logic;
begin
	int : basculeD_reset
		port map(
			H => H,
			RESET => RESET,
			D => aux,
			notQ => aux,
			Q => Q
		);
end behav;

-- 2e methode: sans composant, tout coder directement