VHDL TD 2

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library ieee;
use ieee.std_logic_1164.ALL;

entity full_adder_1bit is
	port( 	A : in std_logic;
		B : in std_logic;
		Re: in std_logic;
		S : out std_logic;
		Rs: out std_logic
	);
end full_adder_1bit;

architecture logic of full_adder_1bit is
begin
	S <= A XOR B XOR Re;
	Rs<= (A AND B) OR (Re AND A) OR (Re AND B);
end logic;

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library ieee;
use ieee.std_logic_1164.ALL;

entity ripple_carry_adder_4bits is
	port( 	A : in std_logic_vector(3 downto 0);
		B : in std_logic_vector(3 downto 0);
		S : out std_logic_vector(4 downto 0)
	);
end ripple_carry_adder_4bits;

architecture behav of ripple_carry_adder_4bits is
	component full_adder_1bit is
		port( 	A : in std_logic;
			B : in std_logic;
			Re: in std_logic;
			S : out std_logic;
			Rs: out std_logic
		);
	end component;
	
	signal R1 : std_logic;
	signal R2 : std_logic;
	signal R3 : std_logic;

begin
	fa0 : full_adder_1bit
		port map(
			A => A(0),
			B => B(0),
			Re => '0',
			S => S(0),
			Rs => R1
		);
	fa1 : full_adder_1bit
		port map(
			A => A(1),
			B => B(1),
			Re => R1,
			S => S(1),
			Rs => R2
		);
	fa2 : full_adder_1bit
		port map(
			A => A(2),
			B => B(2),
			Re => R2,
			S => S(2),
			Rs => R3
		);
	fa3 : full_adder_1bit
		port map(
			A => A(3),
			B => B(3),
			Re => R3,
			S => S(3),
			Rs => S(4)
		);
end architecture;

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library ieee;
use ieee.std_logic_1164.ALL;

entity mul_2bits is
	port(	A,B	: in std_logic_vector(1 downto 0);
		S	: out std_logic_vector(3 downto 0)
	);
end mul_2bits;

architecture struct of mul_2bits is
	component full_adder_1bit is
		port( 	A : in std_logic;
			B : in std_logic;
			Re: in std_logic;
			S : out std_logic;
			Rs: out std_logic
		);
	end component;
	
	signal R1 : std_logic;
	
begin
	S(0) <= A(0) AND B(0);
	fa0 : full_adder_1bit
		port map(
			A => A(1) AND B(0),
			B => A(0) AND B(1),
			Re => '0',
			S => S(1),
			Rs => R1
		);
	fa1 : full_adder_1bit
		port map(
			A => A(1) AND B(1),
			B => '0',
			Re => R1,
			S => S(2),
			Rs => S(3)
		);
end architecture;