VHDL TD 5

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library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;

entity compteur_duree_rebond is
	port(	H		: in std_logic;
		MODULO	: in std_logic_vector(3 downto 0);
		COMPTAGE: in std_logic;
		FIN_COMPTAGE: out std_logic
	);
end compteur_duree_rebond;

architecture behav of compteur_duree_rebond is
	signal Q : integer range 0 to 255;
begin
	process(H) is
	begin
		if(H'event AND H='1') then
			if COMPTAGE='0' then
				Q <= 0;
				FIN_COMPTAGE <= '0';
			else
				Q <= Q+1;
				if Q=to_integer(unsigned(MODULO))-1 then
					Q <= 0;
					FIN_COMPTAGE <= '1';
				end if;
			end if;
		end if;
	end process;
end behav;

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library ieee;
use ieee.std_logic_1164.ALL;

entity sequenceur is
	port(	H, RESET				: in std_logic;
		ENTREE, FIN_COMPTAGE	: in std_logic;
		COMPTAGE, SORTIE		: out std_logic
	);
end sequenceur;

architecture behav of sequenceur is
	signal ETAT : std_logic_vector(1 downto 0);
		--00: Stable_0
		--01: ComptageFM
		--10: ComptageFD
		--11: Stable_1
	signal ETAT_ENTREE_FINCOMPTAGE : std_logic_vector(3 downto 0);
begin
	ETAT_ENTREE_FINCOMPTAGE <= ETAT & ENTREE & FIN_COMPTAGE;
	
	process(H, RESET) is
	begin
		if RESET='1' then
			ETAT <= "00";
		elsif(H'event AND H='1') then
			case ETAT_ENTREE_FINCOMPTAGE is
				WHEN "0010" | "0011" => ETAT <= "01";
				WHEN "0100" | "0101" => ETAT <= "00";
				WHEN "0111" => ETAT <= "11";
				WHEN "1010" | "1011" => ETAT <= "11";
				WHEN "1001" => ETAT <= "00";
				WHEN "1100" | "1101" => ETAT <= "10";
				WHEN others => ETAT <= ETAT;
			end case;
		end if;
	end process;
	
	process(ETAT) is
	begin
		case ETAT is
			WHEN "00" =>
				COMPTAGE <= '0';
				SORTIE <= '0';
			WHEN "01" =>
				COMPTAGE <= '1';
				SORTIE <= '0';
			WHEN "10" =>
				COMPTAGE <= '1';
				SORTIE <= '1';
			WHEN others => --WHEN "11"
				COMPTAGE <= '0';
				SORTIE <= '1';
		end case;
	end process;
end behav;

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library ieee;
use ieee.std_logic_1164.ALL;

entity filtre_anti_rebonds is
	port(	H, RESET, ENTREE: in std_logic;
		SORTIE			: out std_logic
	);
end filtre_anti_rebonds;

architecture behav of filtre_anti_rebonds is
	signal int_FIN_COMPTAGE : std_logic;
	signal int_COMPTAGE : std_logic;
	
	component compteur_duree_rebond is
		port(	H	: in std_logic;
			MODULO	: in std_logic_vector(3 downto 0);
			COMPTAGE: in std_logic;
			FIN_COMPTAGE: out std_logic
		);
	end component;
	
	component sequenceur is
		port(	H, RESET				: in std_logic;
			ENTREE, FIN_COMPTAGE	: in std_logic;
			COMPTAGE, SORTIE		: out std_logic
		);
	end component;
begin
	seq : sequenceur
		port map(
			H => H,
			RESET => RESET,
			ENTREE => ENTREE,
			FIN_COMPTAGE => int_FIN_COMPTAGE,
			COMPTAGE => int_COMPTAGE,
			SORTIE => SORTIE
		);
	
	compt : compteur_duree_rebond
		port map(
			H => H,
			MODULO => "1010", -- =10
			COMPTAGE => int_COMPTAGE,
			FIN_COMPTAGE => int_FIN_COMPTAGE
		);
end behav;