VHDL TD 1

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LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY OUEX IS
	PORT( 	A : IN std_logic;
		B : IN std_logic;
		S1: OUT std_logic;
		S2: OUT std_logic;
		S3: OUT std_logic
	);
END OUEX;

ARCHITECTURE logique OF OUEX IS
BEGIN
	S1 <= (NOT(A) AND B) OR (A AND NOT(B));
	S2 <= A XOR B;
	S3 <= A WHEN B='0' ELSE NOT(A);
END logique;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY concurrence IS
	PORT( 	A : IN std_logic;
		B : IN std_logic;
		C : IN std_logic;
		S : OUT std_logic
	);
END concurrence;

ARCHITECTURE comport OF concurrence IS
	SIGNAL D : std_logic;
BEGIN
	D <= A XOR B;
	S <= D AND C;
END comport;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY mux4to1 IS
	PORT( 	A : IN std_logic;
		B : IN std_logic;
		C : IN std_logic;
		D : IN std_logic;
		COMM : IN std_logic_vector(1 DOWNTO 0);
		S1: OUT std_logic;
		S2: OUT std_logic;
		S3: OUT std_logic
	);
END mux4to1;

ARCHITECTURE logique OF mux4to1 IS
BEGIN
	-- S0 <= (A AND NOT(COMM(1)) AND NOT(COM(0))) OR ...

	S1 <=   A WHEN COMM="00" ELSE B WHEN COMM="01"
		ELSE C WHEN COMM="10" ELSE D WHEN COMM="11"
		ELSE '0';
	
	WITH COMM SELECT
		S2 <= 	A WHEN "00", B WHEN "01",
			C WHEN "10", D WHEN "11",
			'0' WHEN others;
	
	PROCESS(A,B,C,D,COMM) IS
	BEGIN
		CASE COMM IS
			WHEN "00" => S3 <= A;
			WHEN "01" => S3 <= B;
			WHEN "10" => S3 <= C;
			WHEN "11" => S3 <= D;
			WHEN others => S3 <= '0';
		END CASE;
	END PROCESS;
END logique;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY PdsHamm IS
	PORT( 	E : IN  std_logic_vector(3 DOWNTO 0);
		H : OUT std_logic_vector(2 DOWNTO 0)
	);
END PdsHamm;

ARCHITECTURE logique OF PdsHamm IS --FAUX
BEGIN
	H(0) <= E(0) XOR E(1) XOR E(2) XOR E(3);
	H(1) <= ((E(0) XOR E(1)) AND (E(2) OR E(3))) OR
		((E(0) XOR E(2)) AND E(3)) OR
		(E(1) AND E(2) AND (E(0) OR E(3)));
	H(2) <= E(0) AND E(1) AND E(2) AND E(3);
END logique;

ARCHITECTURE comport OF PdsHamm IS
BEGIN
	PROCESS(E) IS
	BEGIN
		CASE E IS
			WHEN "0000" => H <= "000";
			WHEN "0001" => H <= "001";
			WHEN "0010" => H <= "001";
			WHEN "0011" => H <= "010";
			WHEN "0100" => H <= "001";
			WHEN "0101" => H <= "010";
			WHEN "0110" => H <= "010";
			WHEN "0111" => H <= "011";
			WHEN "1000" => H <= "001";
			WHEN "1001" => H <= "010";
			WHEN "1010" => H <= "010";
			WHEN "1011" => H <= "011";
			WHEN "1100" => H <= "010";
			WHEN "1101" => H <= "011";
			WHEN "1110" => H <= "011";
			WHEN "1111" => H <= "100";
			WHEN others => H <= "000";
		END CASE;
	END PROCESS;
END comport;

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library ieee;
use ieee.std_logic_1164.ALL;

entity DstHamm is
	port( 	A : in  std_logic_vector(3 downto 0);
		B : in  std_logic_vector(3 downto 0);
		S : out std_logic_vector(2 downto 0)
	);
end DstHamm;

architecture behav of DstHamm is
	component PdsHamm is
		port( 	E : in  std_logic_vector(3 downto 0);
			H : out std_logic_vector(2 downto 0)
		);
	end component;

begin
	circ : PdsHamm
		port map(
			E(3) => A(3) XOR B(3),
			E(2) => A(2) XOR B(2),
			E(1) => A(1) XOR B(1),
			E(0) => A(0) XOR B(0),
			H => S
		);
end architecture;

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library ieee;
use ieee.std_logic_1164.ALL;

entity comparateur is
	port( 	A : in  std_logic_vector(3 downto 0);
		B : in  std_logic_vector(3 downto 0);
		Ssup : out std_logic;
		Segal : out std_logic;
		Sinf : out std_logic
	);
end comparateur;

architecture behav of comparateur is
begin
	process(A,B) is
	begin
		Ssup <= '0';
		Segal <= '0';
		Sinf <= '0';
		
		if A>B then
			Ssup  <= '1';
		elsif A<B then
			Sinf  <= '1';
		else
			Segal <= '1';
		end if;
	end process;
end architecture;